Which memory element is formed by two cross-coupled NOR gates where a 1 on either input forces the output to 0?

Which memory element is formed by two cross-coupled NOR gates where a 1 on either input forces the output to 0?

• A. R-S Latch
• B. Latch
• C. SR Flip-Flop
• D. J-K Flip-flop

Answer: (A)

Two cross-coupled NOR gates form a simple memory element known as an SR latch. In a NOR latch, the output of each gate goes low when its input is high, and that output feeds the other gate, creating a feedback loop that can hold one of two stable states when both inputs are low. When a 1 is applied to either input, the corresponding gate’s output is forced to 0 due to the NOR truth function. This change propagates through the feedback to set the overall state of the latch (one output becomes 0, the other 1). If both inputs are 0, the feedback maintains the previous state, providing memory without any clocking. This description matches an SR latch built from cross-coupled NOR gates, which is why the R-S Latch is the best answer. The other options refer to different devices (a generic latch, an edge-triggered flip-flop, or a clocked J-K flip-flop) that don’t align with the simple, no-clock SR latch behavior described.

Two cross-coupled NOR gates form a simple memory element known as an SR latch. In a NOR latch, the output of each gate goes low when its input is high, and that output feeds the other gate, creating a feedback loop that can hold one of two stable states when both inputs are low.

When a 1 is applied to either input, the corresponding gate’s output is forced to 0 due to the NOR truth function. This change propagates through the feedback to set the overall state of the latch (one output becomes 0, the other 1). If both inputs are 0, the feedback maintains the previous state, providing memory without any clocking.

This description matches an SR latch built from cross-coupled NOR gates, which is why the R-S Latch is the best answer. The other options refer to different devices (a generic latch, an edge-triggered flip-flop, or a clocked J-K flip-flop) that don’t align with the simple, no-clock SR latch behavior described.